 |
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
| Datasheet File OCR Text: |
| HV214 250V Low Charge Injection 8-Channel High Voltage Analog Switch Features HVCMOS(R) technology for high performance Very low quiescent power dissipation -10A Low parasitic capacitances DC to 10MHz analog signal frequency -60dB typical output off isolation at 5MHz -60dB typical off-isolation at 5MHz CMOS logic circuitry for low power Excellent noise immunity On-chip shift register, latch and clear logic circuitry Flexible high voltage supplies Surface mount packages General Description The Supertex HV214 is a low charge injection 8-channel high voltage analog switch integrated circuit (IC) intended for use in applications requiring high voltage switching controlled by low voltage control signals, such as medical ultrasound imaging, piezoelectric transducer drivers, inkjet printer heads and optical MEMS modules. Input data is shifted into an 8-bit shift register that can then be retained in an 8-bit latch. To reduce any possible clock feedthrough noise, the latch enable bar should be left high until all bits are clocked in. Data are clocked in during the rising edge of the clock. Using HVCMOS(R) technology, this device combines high voltage bilateral DMOS switches and low power CMOS logic to provide efficient control of high voltage analog signals. The device is suitable for various combinations of high voltage supplies, e.g., VPP/VNN: +40V/-210V, +125V/-125V, +210V/-40V. Applications Medical ultrasound imaging Non-destructive evaluation Inkjet printer heads Optical MEMS modules Block Diagram DIN Level Output Latches Shifters Switches D LE CL SW0 D LE CL SW1 CLK D LE CL D LE CL D LE CL D LE CL D LE CL D LE CL SW2 8-Bit Shift Register SW3 SW4 SW5 DOUT SW6 SW7 VDD LE CL VNN VPP HV214 Ordering Information Package Options Device HV214 28-Lead PLCC HV214PJ HV214PJ-G 48-Lead LQFP/ TQFP(1.4mm) HV214FG HV214FG-G Pin Configurations 4 1 25 -G indicates the part is RoHS compliant (Green) 28-Lead (J) PLCC (PJ) (top view) Absolute Maximum Ratings Parameter VDD logic power supply voltage VPP - VNN supply voltage VPP positive high voltage supply VNN negative high voltage supply Logic input voltages Analog signal range Peak analog signal current/channel Storage temperature Power dissipation: 28-Lead PLCC 48-Lead LQFP/ TQFP (1.4mm) Value -0.5V to +15V 260V -0.5V to VNN +250V +0.5V to -260V -0.5V to VDD +0.3V VNN to VPP 2.5A -65OC to +150OC 1.2W 1.0W 48 1 48-Lead LQFP (FG) (7x7x1.4mm) (top view) Product Marking Top Marking YYWW Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is not implied. Continuous operation of the device at the absolute rating level may affect device reliability. All voltages are referenced to device ground. HV214PJ LLLLLLLLLL Operating Conditions Symbol Parameter VDD VPP VNN VIH VIL VSIG TA Logic power supply voltage Positive high voltage supply Negative high voltage supply High level input logic voltage Low-level input logic voltage Analog signal voltage peak-to-peak Operating free air temperature Value 4.5V to 13.2V 40V to VNN +250V -40V to -210V VDD -1.5V to VDD 0V to 1.5V VNN +10V to VPP -10V 0OC to 70OC Bottom Marking CCCCCCCCCCC AAA YY = Year Sealed WW = Week Sealed L = Lot Number C = Country of Origin A = Assembler ID* = "Green" Packaging *May be part of top marking 28-Lead PLCC (PJ) Top Marking YYWW HV214FG LLLLLLLLL Bottom Marking CCCCCCCC AAA YY = Year Sealed WW = Week Sealed L = Lot Number C = Country of Origin A = Assembler ID* = "Green" Packaging *May be part of top marking 48-Lead LQFP (FG) 2 HV214 DC Electrical Characteristics (T Sym Parameter A = 25OC, over recommended operating conditions unless otherwise noted) Min - Typ 23 - Max 55 49 42 36 38 32 20 10 300 500 50 -50 50 -50 2.0 50 7.0 5.0 5.0 -7.0 -5.0 -5.0 10 4.0 10 70 Units Conditions ISIG = 5.0mA ISIG = 5.0mA ISIG = 5.0mA VPP = +40V ISIG = 200mA VNN = -160V VPP = +125V ISIG = 200mA VNN = -100V RONS Small signal switch on-resistance - VPP = +210V ISIG = 200mA VNN = -40V % A mV mV A A A A A kHz ISIG = 5mA, VPP = +125V, VNN = -125V VSIG = VPP - 10V, ISIG = 1A VSIG = VPP -10V & VNN +10V RLOAD = 100K RLOAD = 100K All switches off All switches off All switches on, ISW = 5.0mA All switches on, ISW = 5.0mA VSIG duty cycle 0.1% Duty cycle = 50% VPP = +40V VNN = -160V mA VPP = +100V VNN = -100V VPP = +160V VNN = -40V VPP = +40V VNN = -160V mA VPP = +100V VNN = -100V VPP = +160V VNN = -40V mA A mA mA pF O RONS RONL ISOL Small signal switch On-resistance matching Large signal switch On-resistance Switch off leakage per switch DC offset switch off DC offset switch on - IPPQ INNQ IPPQ INNQ fSW Quiescent VPP supply current Quiescent VNN supply current Quiescent VPP supply current Quiescent VNN supply current Switch output peak current Output switch frequency IPP Average VPP supply current - All output switches are turning ON and OFF at 50kHz with no load INN Average VNN supply current - IDD IDDQ ISOR ISINK CIN TA Average VDD supply current Quiescent VDD supply current Data out source current Data out sink current Large input capacitance Ambient temperature range 45 45 0 fCLK = 5MHz, VDD = 5.0V --VOUT = VDD - 0.7V VOUT = 0.7V ----- C 3 HV214 AC Electrical Characteristics (V Sym tSD tWLE tDO tWCL tSU tH fCLK tR, tF TON TOFF dv/dt Parameter Set-up time before LE rises Time width of LE Clock delay time to data out Time width of CL Set-up time data to clock Hold time data from clock Clock frequency Clock rise and fall times Turn-on time Turn-off time DD = 5.0V, TA = 25OC,over recommended operating conditions unless otherwise noted) Min 150 150 150 15 35 - Typ 8.0 12 38 - Max 150 5.0 50 5.0 5.0 20 20 20 300 17 50 200 200 200 200 200 200 Units Conditions ns ns ns ns ns ns MHz ns s s ------------50% duty cycle, fDATA = fCLK/2 --VSIG = VPP -10V, RLOAD = 10K VSIG = VPP -10V, RLOAD = 10K VPP = +40V, VNN = -160V V/ns VPP = +125V, VNN = -100V VPP = +210V, VNN = -40V dB dB mA pF pF F = 5MHz, 1K//15pF load F = 5MHz, 50 load F = 5MHz, 50 load 300ns pulse width, 2% duty cycle 0V, f = 1MHz 0V, f = 1MHz VPP = +40V, VNN = -210V, RLOAD = 50 mV VPP = +100V, VNN = -125V, RLOAD = 50 VPP = +160V, VNN = -40V, RLOAD = 50 Maximum VSIG slew rate - KO KCR IID CSG(OFF) CSG(ON) +VSPK -VSPK +VSPK -VSPK +VSPK -VSPK Off isolation Switch crosstalk Output switch isolation diode current Off capacitance SW to GND On capacitance SW to GND -30 -58 -60 5.0 25 - Output voltage spike 4 HV214 Truth Table Data in 8-Bit Shift Register D0 L H L H L H L H L H L H L H L H X X X X X X X X X X X X X X X X D1 D2 D3 D4 D5 D6 D7 LE L L L L L L L L L L L L L L L L H X CL L L L L L L L L L L L L L L L L L H OFF OFF Hold Previous State OFF OFF OFF OFF OFF OFF Output Switch State SW0 OFF ON OFF ON OFF ON OFF ON OFF ON OFF ON OFF ON OFF ON SW1 SW2 SW3 SW4 SW5 SW6 SW7 Notes: 1. The eight switches operate independently. 2. Serial data is clocked in on the LH transition CLK. 3. The switches go to a state retaining their present condition at the rising edge of LE. When LE is low the shift register data flows through the latch. 4. DOUT is high when switch 7 is on. 5. Shift register clocking has no effect on the switch states if LE is H. 6. The clear input overrides all other inputs. Logic Timing Waveforms DN+1 DATA IN 50% DN 50% DN-1 LE 50% 50% t WLE t SD 50% 50% th t DO CLOCK t SU DATA OUT 50% t OFF t ON OFF V OUT (TYP) ON 90% 10% CLR 50% t WCL 50% 5 HV214 Test Circuits VPP -10V RL 10K VOUT VOUT VPP -10V ISOL VNN +10V 100K RL VPP VNN VPP VNN VDD GND 5V VPP VNN VPP VNN VDD GND 5V VPP VNN VPP VNN VDD GND 5V Switch OFF Leakage DC Offset ON/OFF TON /TOFF Test Circuit VIN = 10 VP-P @5MHz VSIG VOUT RL IID VNN VIN = 10 VP-P @5MHz 50 NC 50 VPP VNN VPP VNN VDD GND VOUT VIN 5V VPP VNN VPP VNN VDD GND 5V VPP VNN VPP VNN VDD GND VOUT VIN 5V KO = 20Log KCR = 20Log OFF Isolation Isolation Diode Current Crosstalk VOUT VOUT 1000pF +VSPK VOUT -V SPK 50 VSIG 1K RL VPP VNN VPP VNN VDD GND 5V VPP VNN VPP VNN VDD GND 5V Q = 1000pF x VOUT Charge Injection Output Voltage Spike 6 HV214 28-Lead (J-Lead) PLCC (PJ) Pin Description Pin 1 2 3 4 5 6 7 Function SW3 SW3 SW2 SW2 SW1 SW1 SW0 Pin 8 9 10 11 12 13 14 Function SW0 NC VPP NC VNN GND VDD Pin 15 16 17 18 19 20 21 Function NC DIN CLK LE CL DOUT SW7 Pin 22 23 24 25 26 27 28 Function SW7 SW6 SW6 SW5 SW5 SW4 SW4 48-Lead LQFP/TQFP (FG) Pin Description Pin 1 2 3 4 5 6 7 8 9 10 11 12 Function SW5 NC SW4 NC SW4 NC NC SW3 NC SW3 NC SW2 Pin 13 14 15 16 17 18 19 20 21 22 23 24 Function NC SW2 NC SW1 NC SW1 NC SW0 NC SW0 NC VPP Pin 25 26 27 28 29 30 31 32 33 34 35 36 Function VNN NC NC GND VDD NC NC NC DIN CLK LE CLR Pin 37 38 39 40 41 42 43 44 45 46 47 48 Function DOUT NC SW7 NC SW7 NC SW6 NC SW6 NC SW5 NC Power Up/Down Sequence: 1. Power up/down sequence is arbitrary except GND must be powered-up first and powered-down last. 2. VSIG must be VNN VSIG VPP or floating during power up/down transistion. 3. Rise and fall times of power supplies VDD, VPP, and VNN should not be less than 1.0msec. 7 HV214 28-Lead PLCC Package Outline (PJ) .048/.042 x 45O 4 D D1 1 28 26 .056/.042 x 45O 0.150 MAX Note 1 (Index Area) 0.075 MAX E1 E 0.20max 3 Places Top View View B A Base Plane .020 MIN e b Seating Plane A1 A2 Side View Note 1: A Pin 1 identifier must be located in the index area indicated.The Pin 1 identifier may be either a mold, or an embedded metal or marked feature. Symbol A A1 A2 b D D1 E E1 e MIN Dimension (inches) NOM MAX .165 .172 .180 .090 .105 .120 .062 .083 .013 .021 .485 .490 .495 .450 .453 .456 .485 .490 .495 .450 .453 .456 .050 BSC JEDEC Registration MS-018, Variation AB, Issue A, June, 1993. Drawings not to scale. 8 HV214 48-Lead LQFP/TQFP (1.4mm) Package Outline (FG) D D1 E E1 Note 1 (Index Area D1/4 x E1/4) L2 48 1 b e L L1 Seating Plane Gauge Plane Top View View B A A2 Seating Plane A1 View B Side View Note 1: A Pin 1 identifier must be located in the index area indicated. The Pin 1 identifier may be either a mold, or an embedded metal or marked feature. Symbol MIN Dimension NOM (mm) MAX Drawings not to scale. A 1.40 1.60 A1 0.05 0.15 A2 1.35 1.40 1.45 b 0.17 0.22 0.27 D 9.00 BSC D1 7.00 BSC E 9.00 BSC E1 7.00 BSC e 0.50 BSC L 0.45 0.60 0.75 L1 1.00 REF L2 0.25 BSC 0O 3.5O 7O JEDEC Registration MS-026, Variation BBC, Issue D, Jan. 2001. (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information go to http://www.supertex.com/packaging.html.) Doc.# DSFP-HV214 NR050807 9 |
Price & Availability of HV214PJ-G
 |
|
|
|
|
All Rights Reserved © IC-ON-LINE 2003 - 2022 |
| [Add Bookmark] [Contact Us] [Link exchange] [Privacy policy] |
|
Mirror Sites : [www.datasheet.hk]
[www.maxim4u.com] [www.ic-on-line.cn]
[www.ic-on-line.com] [www.ic-on-line.net]
[www.alldatasheet.com.cn]
[www.gdcy.com]
[www.gdcy.net] |